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AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Features
* Operation Voltage 2.5V~6.0V * Oscillation frequency 1MHz * Output Current Maximum 400mADC-DC Converter * Built-In 400mA/LDO * Power Good Indicator with Time Delay Adjustable * Built-In Current Limit * Built-In UVLO * Built-In Thermal ShutDown
General Description
The AT1362A/B provides complete control for a DC/DC converter optimized for high-performance microprocessor applications. It consists of a synchronous step-down DC/DC converter and a high-speed LDO regulator connected in series with the DC/DC converter output. A power good detector and LDO ON/OFF control is also built-in(metal option). DC/DC converter is operated on current mode architecture for excellent line and load transient response. 1MHz operation frequency is allowing the use of small surface mount inductor and capacitor. The internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. The AT1362A/B is a family of low-noise synchronous step-down DC/DC converters that is ideally suited for systems powered form a 1-cell Li-ion battery or from a 3-cell to 4-cell NiCd, NiMH, or alkaline battery. It can also be used to USB-based power system.
Applications
* Power Supply for Slim Type devices
Block Diagram
VBG VBG Vref VREG UVLO VCC
Current Sense
5
AGND
+
SLOPE
+ R S SW Q
OSC Vref + VCC DELAY Auto Discharge 1uA PG UVLO + -
Shoot Throught
BPC
PGND 0.7 R2 R1 OUT1 *OUT1=2.5V/1.8V Metal Option Current Limit R3 + CTL + 0.7V Vref R4 OUT2
Aimtron reserves the right without notice to change this circuitry and specifications.
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 1
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Pin Assignment
1 2 3 4 5
DFN10 (TOP VIEW)
10 9
AT1362A DC/DC 2.5V LDO 3.3V AT1362B DC/DC 1.8V LDO 3.3V
AT1362
8 7 6
Ordering Information
Part Number 1362 N A:1362AN Date Code *For more marking information, contact our sales representative directly. Package DFN10,Green B:1362BN Marking
Pin Description Symbol
1 2 3 4 5 6 7 8 9 10 Bottom
Pin No.
PG OUT1 VCC SW PGND VBG AGND DELAY OUT2 BPC GND
Descript
Power Good Indicator Output(Ative Hi) DC/DC Output (2.5V or 1.8V) Power Supply DC/DC Inductor Node Power Ground Reference Output Voltage Analog Ground The capacitor connection terminal for LDO control and PG delay time setup LDO Output (3.3V) LDO Input By-pass Capacitor Node Analog Ground
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 2
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Absolute Maximum Ratings*1 Parameter
Power Supply Voltage Input Pin Voltage P-Channel Switch Source Current (DC) N-Channel Switch Sink Current (DC) Peak SW Sink and Source Current Thermal Resistance from Junction to Ambient JA Thermal Resistance from Junction to Case JC Operating temperature TA Storage temperature ESD Susceptibility*2
Symbol
VCC OUT1, OUT2 SW, PG -- -- -- DFN10 DFN10 -- -- HBM MM
Rated Value Min. Max.
-0.3 -0.3 -0.3 -20 -20 +6.5 VCC VCC+0.3 0.5 0.5 0.75 35.25 3 +85 +150 2 200
Unit
V V V A A A
0
C/W C/W
0 0
0
C C
KV V
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Device are ESD sensitive. Handling precaution recommended. The Human Body model is a 100pF capacitor discharged through a 1.5K resistor into each pin.
Recommended Operating Conditions
(Ta=+250C)
Parameter
Power supply voltage Operating temperature* Operating junction temperature *Using X5R or X7R input capacitors.
Symbol
VIN TOP TJ
Min.
2.5 -20 -
Values Typ. Max.
-+25 6.0 +85 +150
Unit
C C
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 3
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Electrical Characteristics
(VCC = 3.6V,Ta =+25 , unless otherwise noted. )
Parameter DC/DC CONVERTER
VCC UVLO UVLO Hysteresis width Input Supply Range Quiescent Current Output1 Voltage Accuracy Output1 Voltage line-regulation Output1 Variation with Temperature Feedback current Current Limit Maximum Output Current Oscillator Frequency RDS(ON) of P-Channel MOSFET RDS(ON) of N-Channel MOSFET SW Leakage Current
Symbol
Condition
Values Unit Min. Typ. Max.
2.5 2.4 100 500 0.1 0.5 6 0.7 1.0 200 0.3 0.25 0.1 6.0 +2 0.5 1.0 0.8 1.2 -0.4 0.35 1 V mV V A % % % uA A mA MHz KHz A
VUV VUVHY VCC IS VOUT1
VCC=3V2V Sweep
Active Mode
-2 -
VOUT1-Line VCC=3.5V to 6.0V Ta =-20 to +85 IOUT1 ICL1 IO fosc1 fosc2 RPFET RNFET ISWL VPGON VPGTHYS IPG=1mA VIN=5V, VOUT1=2.5V/1.8V VIN=5V, VOUT1=2.5V/1.8V, L=4.7uH Vout1=2.5V/1.8V Vout1=0V ILX= 300mA ILX= -300mA
0.6 400 0.8 -
CONTROL BLOCK
PG on voltage PG Hysteresis width 0.8 80 80 1.0 0.4 1 1.2 V mV uA mV uA
PG pin leak current IPGTLK VPG=5.0V LDO control on Hysteresis VLDTHYS width DELAY Pin Charge Current IDELAY
LDO
Output2 Voltage Accuracy Current Limit Dropout Voltage Load Regulation Line Regulation Ripple Rejection Rate OUT2 Leakage Current VOUT2 ICL2 VDV VOUT2 LR PSRR IOUT2LK IOUT2=400mA IOUT2=1mA 100mA IOUT2=100mA, VOUT1=3.6V6.0V IOUT2=100mA, f=1kHz -2 450 400 15 0.05 60 6 +2 600 50 0.25 % mA mV mV % dB uA
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 4
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Typical characteristics
Efficiency VS. Output1 Current 100 95 90 85 Efficiency(%)
Efficiency(%) 100 95 90 85 80 75 70 65 60 55 50 Efficiency VS. Output1 Current
80 75 70 65 60 55 50 10 100 Output1 Current(mA) 1000
Vin=5V Vout1=1.8V
L=2.2uH L=3.3uH L=4.7uH L=6.8uH
Vout1=1.8V L=4.7uH
Vin=5.0V Vin=4.2V Vin=3.8V Vin=3.6V
10
100 Output1 Current(mA)
1000
CH1Vin, CH2Vout1 CH3Vout2, CH4PG
CH1DELAY, CH2Vout1 CH3Vout2, CH4PG
CH1Vout1, CH2Vout2, CH4Iout1 Iout1=100mA~300mA, Iout2=200mA
CH1Vout1, CH2Vout2, CH4Iout2 Iout1=200mA, Iout2=100mA~300mA
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 5
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO
Typical Application Circuits
5V
UVLO
90%
2.5V 1.8V VDELY
0.7V
0.7V
90%
3.3V
PG
t1
t2
Timing of Power-On Sequencing
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 6
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Typical Application Circuits ( Continued )
VBG 10nF AGND DELAY 10nF BPC 0.1uF
VCC 10uF 4.7uH SW 10uF
VIN 5.0V
VOUT1 2.5V/400mA
AT1362A
PGND
OUT1 To DSP PG 100K OUT2 VOUT2 3.3V/400mA 2.2uF
Figure 1
VBG 10nF AGND
VCC 10uF 4.7uH
VIN 5.0V
DELAY 10nF BPC 0.1uF
SW 10uF
VOUT1 1.8V/400mA
AT1362B
PGND
OUT1 OUT2
To DSP PG 100K
VOUT2 3.3V/400mA 2.2uF
Figure 2
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 7
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Application Information Capacitor Selection In continuous mode, the source current of the top MOSFET is square wave of duty cycle. The Primary function of the input capacitor is to provide a low impedance loop for the edges of pulsed current drawn by the AT1362A/B. A load step at the output can induce ringing at the input VIN. This ringing can couple to the output and be mistaken as loop instability. The oscillation can be improved by add the capacitance of the input capacitor. A typical value is 10F ceramic (X5R or X7R), POSCAP or Aluminum Polymer. These capacitors will provide good high frequency bypassing and their low ESR will reduce resistive losses for higher efficiency. The input capacitor RMS current varies with the input voltage and the output voltage. The equation for the maximum RMS current in the input capacitor is:
I RMS = I OMAX
VO V (1 - O ) VIN VIN
The output capacitor depends on the suitable ripple voltage. Low ripple voltage corresponds to lower effective series resistance (ESR). The output ripple voltage is determined by:
VOUT I L ( ESR + 1 ) 8 fC OUT
The output capacitor RMS ripple current is given by:
I RMS =
1 VOUT x (VIN - VOUT ) L x f x VIN 23
VBG Capacitor A VBG pin is provided to decouple the bandgap reference voltage. An external capacitor connected form VBG to GND reduces noise present on the internal reference voltage, which in turn significantly reduces output noise and also improves PSRR. Larger capacitor values may be used to further improve PSRR, but result in a longer time period (slower turn on) to settle output voltage when power is initially applied.
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 8
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO LDO For general purposes, use a 2.2uF capacitor on the LDO output. Larger capacitor values and lower ESR provide better supply noise rejection and transient response. A higher value input capacitor may be necessary if large, fast transients are anticipated . Ceramic capacitors have the lowest ESR, and will offer the best AC performance.
When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
Inductor Selection The inductor is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple current. Always consider the losses associated with the DCR and its effect on the total converter efficiency when selecting an inductor. The inductor is selected to limit the ripple current to some predetermined value, typically 20~40% of the full load current at the maximum input voltage. The formula of inductance value is as below:
I L = 0.2 ~ 0.4 x I OUT ( MAX )
L=
VOUT VOUT 1 - f x I L VIN

I PK = I O +
(V - VOUT ) x t ON I L = I O + IN 2 2x L
Power Good Indicator with Adjustable Time Delay When OUT1 pin is above 2.25V or 1.62V (typ.) and with a delay time (t1) the OUT2
is start to regulation. The PG pin terminal is an open drain output of N-MOS. Connect a resistor from PG pin to VCC or OUT2 to create a logic signal. If OUT2 pin is less than 2.97V (typ.) this pin is pulled to ground. When OUT2 pin is above 2.97V (typ.) and with a delay time (t2) this pin is open. PG pin is forced low when in UVLO. The formula of adjustable delay time is as below: 0.7V delay - time = t1 = t 2 = C x I DELAY
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 9
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO The Dissipation The power loss is given by:
2 2 PLOSS ( DC - DC ) = I OUT1 x RDS ( ON ) - P x D + I OUT 1 x RDS (ON )- N x (1 - D) + VIN x I OUT1 x (t r + t f ) x f s + I s x VIN
PLOSS ( LDO ) = I OUT 2 x (VIN - VOUT 2 )
TJ ( MAX ) = T A + JA x ( PLOSS ( DC - DC ) + PLOSS ( LDO ) )
Inductance(H) 3.3 4.7 3.3 3.3 4.7
Inductors Surface Mount Manufacturer/Part No. Sumida CDRH4D28-3R3 Sumida CDRH5D18-4R7 Mitsumi C3-K1.8L-3R3 Mitsumi C4-K1.8L-3R3 ABC SH40283R3YSB ABC SH40284R7YSB Capacitors Surface Mount Manufacturer/Part No. TDK C3216X5R0J226M TDK C3225X5R0J46M GRM42-6X5R 106K6.3 TAIYO LMK212BJ225MD TAIYO JMK212BJ475MG
Manufacturer Website www.sumida.com www.mitsumi.co.jp www.atec-group.com
Capacitance(F) 22 47 10 2.2 4.7
Manufacturer Website www.tdk.com www.tdk.com www.murata.com www.t-yuden.com www.t-yuden.com
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 10
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO PC Board Layout
1. The most critical aspect of the layout is the placement of the input capacitor C2. It must be placed as close as possible to the AT1362A/B to reduce the input ripple voltage. 2. Power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. The longer and narrower the trace, the higher resistance and inductance it will have. The length of traces in series with the capacitors increases its ESR and ESL and reduces their effectiveness at high frequency. 3. The OUT1 pin should connect to C1 directly. And the route should be away from the noise source, such as inductor of SW line. 4. Grounding all components at the same point may effectively reduce the occurrence of loop.
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 11
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Package Outline : DFN10
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw 12
AT1362A/B
Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO Reflow Condition (IR/Convection or VPR Reflow)
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat -Temperature Min(Tsmin) -Temperature Max (Tsmax) -Time (min to max)(ts) Time maintained above: -Temperature (TL) -Time (tL) Peak/Classification Temperature(TP) Time within 5C of actual Temperature (tP) Ramp-down Rate Time 25C to Peak Temperature Peak Sn-Pb Eutectic Assembly 3C/second max. Pb-Free Assembly 3C/second max.
100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max.
150C 200C 60-180 seconds 217C 60-150 seconds See table 2 10 seconds max. 6C/second max. 8 minutes max.
*All temperatures refer to topside of the package, measured on the package body surface.
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process -Package Peak Reflow Temperatures Package Thickness <2.5mm 2.5mm Volume mm <350 240+0/-5 225+0/-5
3 3 3
Volume mm 350 225+0/-5 225+0/-5
3
3
Table 2. Pb-free Process -Package Classification Reflow Temperatures Package Thickness <1.6mm 1.6mm - 2.5mm 2.5mm Volume mm <350 260+0 260+0 250+0 Volume mm 350-2000 260+0 250+0 245+0 Volume mm >2000 260+0 245+0 245+0
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0. For example 260+0) at the rated MSL level.
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